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71 IP
51
1.0
WD28 / SC28: sub 80fF ESD Macro for multi-gigabit SerDes, TSMC 28nm
A silicon-proven, ultra-low-capacitance ESD macro in TSMC 28nm for multi-gigabit SerDes, available in wirebond (WD28) and flip-chip (SC28) variants. I...
52
1.0
MS55: Multi-voltage analog I/O Library with custom 12V ESD, GlobalFoundries 55nm BCD Lite
A silicon-proven, flip-chip-optimized analog and mixed-signal I/O library in GlobalFoundries 55nm BCD Lite, providing 1.8V, 3.3V, 5V, and 12V analog I...
53
1.0
IS55: Specialized 20V Analog ESD Cell, TSMC 55nm LP
A silicon-proven 20V ESD protection cell in TSMC 55nm LP, built for high-voltage interfaces in analog, mixed-signal, RF, and power-management ICs. Its...
54
1.0
5V ESD Clamp in GlobalFoundries 180nm LPe
5V, ESD clamp in GlobalFoundries 180nm that can be used for either signal protection or 1.8V Power supplies. The clamp is a compact single cell, 44um ...
55
1.0
AV55: Low-Capacitance RF ESD Cell Library, TSMC 55nm LP
A production-quality, silicon-proven ESD library in TSMC 55nm LP — not a full I/O, but a collection of standalone, low-capacitance ESD cells for RF an...
56
0.118
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library...
57
0.118
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library...
58
0.118
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library...
59
0.118
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library...
60
0.118
UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library...
61
0.118
UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library
UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library...
62
0.118
UMC 90nm LL-RVT (Low-K) Process with 3.3V device analog esd IO group (with BOAC)
UMC 90nm LL-RVT (Low-K) Process with 3.3V device analog esd IO group (with BOAC)...
63
0.118
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
64
0.118
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
65
0.118
UMC 90nm SP/RVT Low-K process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm SP/RVT Low-K process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
66
0.118
UMC 90nm SP/RVT process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm SP/RVT process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
67
0.0
SD 3.0 I/O Pad Set
The SD library provides the driver / receiver cell and required support cells for SD 3.0 signaling. Fault-tolerant operation. This library is offere...
68
0.0
RGMII IO Pad Set
The (R)GMII library provides the combo driver / receiver and required support cells for (R)GMII signaling. The libraries are compliant with the Gigabi...
69
0.0
ONFI IO Pad Set
The ONFI library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to support bo...
70
0.0
SSTL_15_18 IO Pad Set
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since t...
71
0.0
subLVDS IO Pad Set
The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_450_18V_T is a 1400MBit/s LVDS Driver, LDP_IN_450_18V_DN is a 14...
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